What process node will AMD Zen 7 use?

AMD Zen 7 'Grimlock' compute-die tiles are slated for TSMC's 1.4nm A14 process, with mass production targeted for 2028. The A14 node delivers approximately 10-15% logic-density improvements over N2P at iso-power, with backside power delivery as the architectural lever.

What is Powertech FOPLP packaging?

Powertech Technology Corporation's fan-out panel-level packaging (FOPLP) uses rectangular 600mm by 600mm substrates instead of circular 300mm wafers, lifting usable area per panel by close to 4x versus traditional fan-out wafer-level packaging. AMD is evaluating it as a second-source alternative to TSMC's CoWoS for Zen 7.

How many cores will AMD Zen 7 Grimlock have per CCD?

Each Grimlock compute-core die is expected to carry 16 cores and pair with 3D V-Cache stacks of up to 224MB L3 — roughly 75% more cache capacity than current Zen 5 EPYC parts.

Why is AMD diversifying packaging beyond TSMC CoWoS?

CoWoS supply has been the binding constraint on every advanced AMD, Nvidia, and Broadcom product for two years. Validating FOPLP on Zen 7 would give AMD a non-TSMC packaging path at a flagship server tier for the first time, providing a structural hedge against the bottleneck that has defined the current cycle.

Packaging

AMD Zen 7 Targets TSMC A14 With Powertech FOPLP Packaging

May 27, 2026 | By SBN Media Studio | Taipei, Taiwan

AMD Zen 7 Grimlock CCD wafer on TSMC A14 1.4nm process beside Powertech fan-out panel-level packaging substrate marking the May 27 2026 supply-chain disclosure

MAY 27, 2026 — TAIPEI, TAIWAN. AMD has selected TSMC's 1.4nm A14 process for the compute-die tiles of its next-generation Zen 7 'Grimlock' server CPUs and is actively evaluating Powertech Technology Corporation's fan-out panel-level packaging as a second-source alternative to TSMC's CoWoS platform, according to a supply-chain report from TrendForce. The disclosure, corroborated by Wccftech, VideoCardz, and TechPowerUp, locks AMD into the angstrom era and signals the first credible attempt by a flagship logic customer to diversify advanced packaging beyond TSMC's in-house line.

Zen 7 is positioned for 2028 mass production, slotting in roughly two years after Zen 6 'Venice' on N2P and aligning with TSMC's accelerated angstrom roadmap. Tom's Hardware reported earlier this month that TSMC has formalized A14 as a flagship 2028 node, with pilot wafers running through Fab 25 Phase 1 in Taichung from 2027 before high-volume conversion. Each Grimlock compute-core die is expected to carry 16 cores and pair with 3D V-Cache stacks of up to 224MB L3 — a roughly 75% capacity lift over current Zen 5 EPYC parts and a direct response to Nvidia's coherent-cache memory dominance in AI training racks. Wccftech reports the Grimlock CCDs will pair with separate I/O dies fabricated on a mature trailing node, preserving the chiplet disaggregation model that has carried AMD through Zen 4 and Zen 5 while concentrating leading-edge wafer spend on the compute tiles that justify the A14 premium.

The packaging story is the more disruptive thread. CoWoS supply has been the binding constraint on every advanced AMD, Nvidia, and Broadcom product for two years, and Powertech's fan-out panel-level approach uses rectangular 600mm by 600mm substrates rather than circular 300mm wafers, lifting useable area per panel by close to 4x versus traditional fan-out wafer-level packaging. Validating FOPLP on Zen 7 would give AMD a non-TSMC packaging path for the first time at a flagship server tier and put pressure on Amkor, ASE, and SPIL to accelerate their own panel-level investments. VideoCardz notes Powertech is also working with Broadcom and MediaTek on parallel FOPLP qualifications, which would broaden the supplier base faster than CoWoS expansions can absorb 2027 demand. TechPowerUp adds that AMD's IP roadmap explicitly contemplates dual-sourcing the packaging tier — a contractual stance Nvidia has historically resisted in favor of CoWoS exclusivity, and one that gives AMD an asymmetric cost lever heading into the 2028 server refresh cycle.

The strategic stakes extend beyond AMD. A successful FOPLP qualification at a flagship server tier would re-rate every OSAT competitor that has so far treated panel-level packaging as a mid-range or RF play. It would also give Intel, which is pursuing its own glass-substrate packaging roadmap, a direct competitive benchmark for cost and yield. TrendForce flags warpage control, redistribution-layer lithography, and panel-handling tooling as the three open engineering questions Powertech still needs to close before high-volume A14 silicon can ride on FOPLP carriers — none of them new problems, but all three unresolved at the volumes a Zen 7 EPYC ramp would require.

The competitive read across the rest of the angstrom roadmap is also sharpening. TSMC's A14 currently carries node-on-node logic-density gains in the 10% to 15% range over N2P at iso-power, with backside power delivery as the architectural lever that drives most of the improvement. AMD's commitment to A14 for Zen 7 confirms the company will not skip a node to wait for A10, contradicting earlier supply-chain speculation that the EPYC roadmap would pause at N2P. The decision keeps AMD on a steady two-year cadence and aligns its server refresh with Nvidia's expected Rubin Ultra and Feynman generations on the same TSMC platform, ensuring AMD enters the 2028 AI-server window with a process-parity product rather than a node-trailing one.

The combined A14 plus FOPLP commitment positions AMD to ship a 2028 server platform that is both node-leading and packaging-diversified — a structural hedge against the bottleneck that has defined the current cycle. Whether Powertech clears AMD's reliability gates over the next 18 months will determine if CoWoS lock-in finally breaks or simply bends, and whether the angstrom era opens with one packaging supplier or three.