SK Hynix Pushes HBM4 Capacity Expansion to Q3 as AI Memory Supercycle Tightens

SK Hynix has confirmed it is pushing the second phase of its HBM4 capacity expansion from Q2 to Q3 2026, even as its world-first HBM4 mass production line came online at the M16 Icheon and M15X Cheongju fabs in February 2026. The delay reflects the difficulty of stepping logic-on-memory base dies — produced for SK Hynix by TSMC on a 12nm logic process — through high-volume packaging while NAND and DRAM capex is being rebalanced toward 300+ layer 3D NAND in parallel, according to DigiTimes.

HBM4 doubles the I/O count to 2,048 bits per stack and lifts bandwidth and power efficiency by more than 40% over HBM3E — the architectural step that NVIDIA, AMD and Broadcom have been waiting for to feed agentic-AI training clusters. SK Hynix's monthly DRAM wafer capacity now stands at roughly 160,000 wafers, but a meaningful share is being reallocated to HBM, where prices and margins are running well above commodity DRAM and where the company has already pre-sold most of its 2026 output to hyperscaler-grade AI accelerator customers.

The market context is competitive. Samsung and Micron also formally entered HBM4 mass production this year, and all three are now bidding for NVIDIA's expanded 16-Hi HBM4 orders that will accompany Vera Rubin and Rubin Ultra accelerators. Industry consultants surveyed by DigiTimes describe 2026 as an outright HBM memory supercycle, with hyperscaler demand for HBM4 already pre-allocated for the full year and HBM4E sampling expected before year-end. The Q3 delay therefore tightens, rather than loosens, the squeeze on memory supply for AI build-outs.