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Huawei Ascend 950PR inference accelerator on a Shenzhen industrial backdrop with a Tau Scaling Law LogicFolding architecture diagram beside an NVIDIA H20 reference comparison for June 1 2026
Semiconductors

Huawei Ascend 950PR + 'Tau Scaling Law' Challenge NVIDIA

Huawei's Ascend 950PR hits 1.56 PFLOPs at ~2.8x H20 FP4 throughput on SMIC N+2, paired with a new Tau Scaling Law architecture targeting $12B AI-chip revenue in 2026.

NVIDIA Constellation Taipei headquarters campus rendering in the Beitou-Shilin district beside a TSMC CoWoS silicon interposer wafer and a Vera Rubin NVL72 rack silhouette

NVIDIA Plants Flag in Taipei: Constellation HQ + CoWoS Lock

NVIDIA pre-commits >50% of TSMC CoWoS capacity through 2027 for Vera Rubin and unveils Constellation, a 50-year-lease Taipei HQ targeted for full ops by 2030.

Exploded view of an HBM4E stack showing 12-Hi DRAM dies bonded to a TSMC 3nm base die beside a Samsung 4nm comparison wafer for the June 1 2026 announcement

SK Hynix Bets TSMC 3nm for HBM4E Logic Die

SK Hynix is moving HBM4E base-die fabrication to TSMC 3nm, widening the gap with Samsung's 4nm just as NVIDIA opens 16-Hi HBM4 orders and SK Hynix holds ~62% share.

AMD Zen 7 Grimlock CCD wafer on TSMC A14 1.4nm process beside Powertech fan-out panel-level packaging substrate marking the May 27 2026 supply-chain disclosure

AMD Zen 7 Targets TSMC A14 With Powertech FOPLP Packaging

AMD Zen 7 'Grimlock' CCDs are slated for TSMC 1.4nm A14 with Powertech FOPLP packaging under evaluation, signaling the first credible break from CoWoS for 2028.

Rapidus IIM-1 Chitose Hokkaido fab with a 2nm gate-all-around test wafer and Canon plus Synopsys logos marking the May 27 2026 first-customer milestone

Rapidus 2nm Pilot Lands Canon, 60 Customers in Talks

Japan's Rapidus has begun 2nm gate-all-around pilot wafers at IIM-1 with Canon as first paying customer and 60+ firms in commercial discussions ahead of 2027 ramp.

SK Hynix HBM4E stack beside a soaring Seoul share-price chart and Microsoft Google Amazon hyperscaler logos marking the May 27 2026 Asia-third-largest-company milestone

SK Hynix Becomes Asia's 3rd-Largest Co. on HBM Supercycle

SK Hynix shares up 186% YTD at 1,680,000 won as Microsoft, Google, and Amazon offer to bankroll HBM capacity expansion. Q1 operating margin of 72% tops Nvidia.

ASML High-NA EUV lithography tool with a 0.55 NA optical column, an etched 8nm-pitch test wafer and Intel and SK Hynix fab silhouettes marking the May 19 2026 commercial-readiness milestone

ASML Says First High-NA EUV Chips Arrive in Months as Intel and SK Hynix Lead Adoption

ASML chief executive Christophe Fouquet told the imec Future Summit in Antwerp on May 19, 2026 that the first commercial chips produced on the company's next-ge

Intel 18A wafer in a foundry cleanroom with a monthly yield curve climbing 7-8 percent and customer logos blurred behind CEO silhouette marking the May 18 2026 foundry turnaround update

Intel 18A Yields Climb 7-8% Monthly as Foundry Books Multiple New Customers

Intel chief executive Lip-Bu Tan told CNBC on Monday, May 18, 2026 that the company's foundry turnaround is now visible in the numbers, with 18A process yields

TSMC CoWoS advanced packaging interposer with 12 HBM stacks beside an AI accelerator wafer and a 98 percent yield chart marking the May 14 2026 Hsinchu symposium disclosure

TSMC CoWoS Yields Reach 98% as AI Packaging Capacity Doubles in 2026

TSMC told customers at the Hsinchu session of its 2026 Technology Symposium on May 14, 2026 that CoWoS advanced-packaging yields are now above 98% across its vo

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